1. Field of the Invention
The present invention relates to a semiconductor composite structure, and more particular to a semiconductor composite structure which includes a combination of a silicon-on-insulator (SOI) structure, wherein a thin silicon layer, i.e., a Si over-layer, is separated from the substrate by an insulating region, and a silicon-on-nothing (SON) structure, where the Si over-layer is separated from the substrate by an extended void plane or air gap. The present invention also relates to methods for forming the aforementioned semiconductor composite structure.
2. Background of the Invention
In microelectronic integrated circuit (IC) fabrication, SOI and SON wafers are used in instances where a particular IC requires that the active device regions be separated and isolated from the underlying semiconductor substrate. When the active device regions, which are relatively small in physical dimensions and volume, are kept in contact with the substrate, which is vastly larger in volume, various effects deleterious to the device and circuit performance are observed. For example, the following effects may be observed: increased leakage current and junction capacitance, reduced resistance to effects of radiation and heat, increased short-channel effects, and increased vulnerability to electrical disruption called latch-up. In all, these deleterious effects translate to loss of device and circuit performance and the increase in power consumption.
The SOI and SON devices and circuits, by virtue of the unique semiconductor material structure on which they are built, are essentially immune from the above-mentioned effects and are thus in great demand.
In SOI, a continuous layer of buried insulating material such as an oxide is formed between a Si over-layer and a semiconductor substrate. The buried insulating material serves to electrically isolate the Si over-layer from the substrate. In a proven method referred to as bond-and-etch-back SOI (BESOI), this is achieved by oxidizing two starting semiconductor wafers on the surface, bonding the two wafers at the oxidized surfaces, and then reducing one wafer to a thin over-layer by etching it down from the backside and polishing the etched wafer to provide a smooth surface that is suitable for device fabrication. Since the wafer surfaces are oxidized to a desired depth prior to bonding, very good control of the buried oxide formation can be maintained. Hence, the resulting buried oxide is very uniform and can have nearly any desired thickness. However, trapping of impurities at the bonded interface and the difficulty in achieving a thin, uniform Si over-layer through etch-back process are major weaknesses of prior art BESOI processes.
In another proven method called SIMOX (separation by ion implantation of oxygen), oxygen ions are implanted directly into a wafer surface and then the implanted oxygen ions are reacted with Si atoms to form a buried oxide layer upon annealing at a high temperature. The depth, thickness, and uniformity of the buried oxide layer is primarily dependent on the dose and energy of the implanted oxygen and the subsequent annealing conditions. Generally, SIMOX processes provide buried oxides and a Si over-layer that are uniform and are of high-quality.
In yet another proven method called FIPOS (full isolation by porous oxidized silicon), a patterned Si surface is anodized in a HF-containing solution to form porous Si fully surrounding unanodized Si islands. In this method, the Si islands are patterned and converted to a type resistant to anodization prior to insertion into the solution. As the porous Si oxidizes so much faster than bulk Si, due to its vastly increased surface area, it fully surrounds and isolates the Si islands upon thermal oxidation. This prior art method is regarded as a very inexpensive way of forming SOI. However, it is generally difficult to form thin and yet very dense thermal oxides with this prior art method. Moreover, the Si islands may suffer from dislocations and stacking faults, if it is stressed by the surrounding oxidized porous Si.
In SON, an extended void plane or air gap is formed underneath the Si over-layer surface. By necessity, however, the buried void plane is finite in lateral dimension, as the Si over-layer and the semiconductor substrate below would separate if the void plane were to extend to the full diameter of the semiconductor wafer. Usually, buried void planes of limited size are formed at select locations on the wafer.
In a further proven prior art method referred to as empty space in silicon (ESS), elongated etch-pits are formed on the wafer surface and are transformed into a buried void plane by annealing in a hydrogen ambient at elevated temperatures, which induce the surface migration of Si atoms. The area and thickness of the buried void plane and the Si over-layer above are determined by the width and depth of the individual etch-pits as well as the pitch and the number of the etch-pits.
In yet another further proven method, a SiGe layer is deposited on a semiconductor wafer surface by selective epitaxial growth, a Si bridge is formed above the SiGe layer, and then the SiGe layer is selectively etched away, leaving an air gap. In this prior art method, the whole procedure is incorporated as a part of the device fabrication process.
As the known prior art methods for fabricating SOI and SON composites are quite different, and because the former involves buried oxide and the latter a void, it has not been practical so far to combine the two composite structures on a single semiconductor wafer. In terms of low-power device isolation, the SON composite is far superior in that the dielectric constant of a void typically approaches 1, the lowest possible dielectric constant, while the dielectric constant of a typically buried oxide such as SiO2 is about 3.9.
In addition to device isolation, however, the buried insulating region, if properly patterned, can perform additional function as a back-gate dielectric, while the SON can be used as a compliant substrate for lattice-mismatched epitaxial layers, such as SiGe and GaAs. Thus, a SOI/SON composite combination may not only improve the microelectronic applications that currently utilize the SOI and SON separately, but also the composite combination may be useful in many new applications that are not presently known or yet realized.
The present invention provides a method to form a patterned SOI/SON composite structure on a single semiconductor wafer by a shared process. A key feature of the inventive shared process is the formation of a porous Si layer by electrolytic anodization in a HF-containing solution. In some prior art SOI methods, porous Si is used as a sacrificial etch-stop, a splitting plane, a field oxide region or a full-isolation oxide region. In the present invention, however, the porous Si is uniquely utilized in forming a buried insulating/void combination.
As such, a principal objective of the present invention is to provide a semiconductor composite structure that includes a patterned SOI/SON structure. The composite structure may include single or multiple levels of SOI and SON structures. In the present invention, the patterned SOI/SON structures, in a given layer, are formed adjacent to each other, in an alternating pattern of SOI and SON.
Another objective of the present invention is to provide a method to fabricate such SOI/SON-containing composites.
A further objective of the present invention is to provide a method to fabricate such SOI/SON-containing composites that includes processing steps that are mostly shared by both SOI and SON structures.
A still further objective of the present invention is that the SOI/SON structural pattern is not fixed, but can be formed in any desired shape and size.
In accordance with one aspect of the present invention, a semiconductor composite structure, which includes a combination of patterned SOI and SON structures, is provided. Specifically, the inventive semiconductor composite structure comprises:
a semiconductor substrate;
one or more layers of patterned buried insulating regions and void planes located next to each other and atop the semiconductor substrate; and
a Si over-layer of a predetermined thickness located atop the one or more layers of patterned buried insulating regions and void planes.
In one embodiment of the present invention, the buried insulating regions of the inventive semiconductor composite structure are replaced with a buried conductive region. In another embodiment of the present invention, the inventive semiconductor composite structure includes only void planes. In yet another embodiment of the present invention, the inventive semiconductor composite structure includes buried insulating regions, buried conductive regions, and void planes.
In accordance with another aspect of the present invention, a method of forming the above-mentioned semiconductor composite structure is provided. Specifically, the method of the present invention comprises the steps of:
(a) forming a layer of porous Si in a surface region of a semiconductor wafer;
(b) forming an epi-Si layer on the layer of porous Si, wherein an interface exists between the epi-Si layer and the layer of porous Si;
(c) selectively implanting ions into predetermined areas of the wafer to form implant regions at or near said interface; and
(d) annealing the wafer at an elevated temperature which causes transformation of the implant regions, by reaction with the surrounding layer of porous Si, into buried insulating regions, and transformation of unimplanted porous Si, by pore coalescence, into buried void planes.
In some embodiments of the present invention wherein multilayers of vertically stacked buried insulating/void planes are formed, steps (a)-(c) are repeated any number of times prior to performing annealing step (d).
In accordance with the present invention, the porous Si layer is formed by utilizing electrolytic anodization that is performed in a HF-containing solution. In HF-anodization, the porosity of the porous Si formed is mainly dependent on the current and voltage used, the HF concentration, and the doping type and concentration of the semiconductor wafer. The thickness of the porous Si layer, in addition, depends on the time of the anodization process.
A brief anneal in a hydrogen ambient at an elevated temperature may be employed after step (a), if necessary, to eliminate open pores on the surface of the porous Si layer. In yet another embodiment, an optional hydrogen anneal is also performed after annealing step (d).
In some embodiments, a patterned mask of silicon dioxide, silicon nitride, photoresist or a combination thereof may be employed to selectively form the implant regions in the wafer. In such an embodiment, the patterned mask has a sufficient thickness that prevents ions from being implanted into the regions of the structure where void planes are to be formed.
In an alternative method of the present invention, the ions that are implanted are capable of forming a buried conductive region upon annealing. In such an embodiment, metal ions are implanted and the buried conductive regions include metal silicides.
In a yet further alternative method of the present invention, a composite structure including buried void planes only is provided. This method of the present invention comprises the steps of:
(i) forming a patterned mask of HF-resistant material, e.g., photoresist, atop a semiconductor wafer, said patterned mask having one or more openings that expose portions of said semiconductor wafer;
(ii) forming porous Si in surface regions of said exposed portions of said semiconductor wafer;
(iii) removing said patterned mask;
(iv) forming epi-Si atop the wafer including said porous Si; and
(v) annealing the wafer at an elevated temperature which causes transformation of the porous Si, by pore coalescence, into buried void planes.
In another alternative method of the present invention, a semiconductor composite structure containing buried layers of insulator/void plane structures side-by-side, conductor/void plane structures side-by-side, and void plane structures alone is provided by repeating steps (a)-(c) and steps (i)-(iv) of the aforementioned methods any number of times prior to performing the final anneal step which cause the above-mentioned transformations.